Network MCUs optimise for data throughput

NXP Semiconductors has extended its family of ARM7-based MCUs featuring the unique twin-AHB architecture that enhances CPU utilisation and throughput.

The latest members, the LPC2365 and LPC2367, integrate an Ethernet MAC and up to 512kbytes of Flash. The twin AHBs enable simultaneous Ethernet DMA and programme execution from the on-chip memory without impacting the main application.

Additional features to maximise throughput include 128-bit memory-interface width and a unique accelerator architecture, which enables 32-bit code execution at the 72MHz maximum clock rate.

Both devices include connectivity-focused peripherals including an Ethernet port with DMA, as well as four UARTs, three I²C bus interfaces and an I2S interface. A general-purpose DMA controller is also implemented on the AHB. This can be used with the SSP serial interfaces, the I2S port and SD/MMC card interface provided on the LPC2367, as well as for memory-to-memory transfers. A bus bridge supports connectivity between the two AHB domains.

Further integrated memory resources include up to 32kbyte of SRAM on the ARM local bus for high-performance CPU access, 16kbyte SRAM for the Ethernet interface and 8kbyte SRAM for the general-purpose DMA. There is also a 2kbyte SRAM powered from the RTC clock, allowing data to be stored when the rest of the chip is powered off.

 

FEATURES 70 GPIO pins with configurable pull-up/down resistors 32-level Vectored Interrupt Controller (VIC) Power-management modes On-chip PLL Boot loader for rapid Flash programming

APPLICATIONS Industrial control systems Point-of-Sale (POS) equipment Building automation Security systems

 

 

NXP LPC2365/7 ARM7 MCUs