Using power-management innovations of emerging MCUs

To help embedded-systems designers meet ambitious energy-efficiency targets, emerging MCUs are implementing extra functions to support ultra-responsive power management. This article explains how engineers can use innovative clock-management features and multiple CPU operating modes to achieve system-level power savings.

 

Clock selection and distribution

Control over operating frequency is fundamental to maximising power efficiency in embedded systems. The latest MCUs provide numerous opportunities for engineers to optimise clocking of the CPU and individual modules to minimise current draw and meet system-level performance requirements.

 

 

The Internal Clock Source (ICS) module implemented in the Freescale Semiconductor MC9S08QE128 provides an example. The ICS enables designers to select an external reference clock (ERCLK) from 32kHz up to 16MHz, or an internal reference clock (IRCLK) that can be trimmed from 31.25kHz to 39.06kHz. Figure 1 illustrates the internal structure of the QE128 ICS.

 

 

Key elements include the Frequency Locked Loop (FLL) block and a set of programmable dividers and trimmers, as well as integrated clock-enable logic that help optimise clock selection and distribution. Table 1 shows the clock sources that are available to each module on the MC9S08QE128. Other clocks shown in the table are OSCOUT and XCLK. OSCOUT is a direct path to the external clock. XCLK is the signal going into the FLL block, which may be either the internal oscillator or a divided version of the external clock source.

As a secondary power-saving feature, clock-gating registers allow clocks to unused modules to be gated off to reduce current draw in Run and Wait modes. Best-practice guidelines when using clock-gating features include gating clocks off as soon as possible after a reset to maximise power savings, since the reset signal will gate all clocks on. Disabling modules before gating off, and reinitialising when the module is gated back on is also recommended, to guard against erroneous operation.

 

Optimising clock mode

Since the MC9S08QE128’s ICS is routed to all the power-consuming and component-controlling peripherals, designers can optimise power and performance on a per-module basis. The ICS has six modes of operation, allowing use of a low-power external oscillator if desired, or disabling or bypassing of the FLL if appropriate.

 

CPU-mode selection

In addition to providing extra clock-management opportunities such as those supported by the MC9S08QE128 ICS, modern power-conscious MCUs also provide a variety of CPU operating modes. Along with the usual Run mode, the MC9S08QE128 has five reduced-power modes that deliver various degrees of power savings but also impose certain restrictions in terms of exit path, wake-up time and register retention.

Wait mode saves between 30-60% of the MCU’s Run-mode current, depending on the bus frequency, by shutting down the CPU while maintaining the MCU’s system clocks and full voltage regulation. Any interrupt will allow Wait mode to be exited instantly.

There are also two Stop modes that halt the system clocks and place the voltage regulator into standby, to further reduce power consumption. Stop 3 mode has a fast wake-up time of 6µs, while Stop 2 powers down the internal circuits for extra savings while maintaining the RAM contents and pin states. One trade-off, however, is that exit paths are restricted. While signals from certain functional blocks can trigger exit from Stop 3 mode, Stop 2 is only exited upon receipt of a Reset, IRQ or RTC.

In addition, the MC9S08QE128 implements Low Power Run (LPR) and Low Power Wait (LPW) modes. LPR saves power compared to normal Run mode by placing the voltage regulator into standby. LPW mode can only be entered from LPR mode, but can typically save 50% of the LPR current consumption.

 

 

Table 2 compares the key characteristics of the CPU operating modes.

 

Conclusion

By carefully selecting and using the multiple CPU operating modes of next-generation MCUs such as the Freescale MC9S08QE128, in addition to controlling the clock source, clock distribution and clock operating modes, designers can maximise the MCU’s contribution to power savings in modern consumer and industrial products.

 

 

Development board CrossBow is available to members of the Future Board Club. To apply for the development board, and membership of the Board Club, go to www.my-boardclub.com/manf-offers.htm This offer is free and subject to qualification.

 

Freescale Power Management Design Note