Designing for long-term SRAM performance

These guidelines are a selection of smart electrical engineering practices that can lead to excellent long-term SRAM system performance.

Decoupling (bypass) capacitors

Decoupling capacitors, or bypass caps, are often the most confusing component in a high-speed digital design. Additionally, as the speed of signals increases, many older designs using the same decoupling methodology need to be updated.

In simple terms, the reason systems need decoupling capacitors is to reduce the amount of noise in the power system, by eliminating the effects of inductance on the power-supply bus. The capacitor’s low series resistance and series inductance, should decouple or bypass the power-supply bus from the IC. This prevents voltage swing on the power and ground pins, provides a low impedance path from the power plane to the ground plane, and provides a signal return path between the power and ground planes.

An important function of the decoupling capacitor is to eliminate the effects of inductance. To explain why, consider the equation below:

 

This equation states that a change or surge in the current taken across a finite inductance will cause an increase in voltage. Generally, when an IC is behaving statically, the wiring inductance is not a problem and there is no additional voltage (noise) on the power lines. When the outputs of the IC switch, however, there will be a surge in current as the IC attempts to drive different voltage levels, adding significant noise to the power lines.

Figure 1 shows the simplified schematic of an SRAM output.

 

 

The inductors that are shown represent the wiring inductance between the die of the device and the power plane. When transistor Q1 is on and transistor Q2 is off, the output goes to a high voltage level. When Q2 is on and Q1 is off, the output is tied to ground and therefore a low voltage level.

At the moment that Q2 turns on and Q1 turns off, a spike of current flows from the output to the ground through transistor Q2. This changing current also flows through the intrinsic and wiring inductance shown and, in accordance with equation above, changes the voltage at Reference B. In other words, as Q2 turns on and the voltage at the output begins to drop, the voltage at Reference B (which, ideally, would be 0V) will actually rise due to the current spike. Thus, the output voltage (V_OUT) does not fall all the way to zero as it should, but rather bounces above a grounded voltage level. This is known as ground bounce. A similar effect will be seen at Reference A when Q1 switches on and the current spike drives the output high. In this case, the ending value of V_OUT will be below supply voltage (V_DD), known as voltage droop.

 

Picking the right capacitor

To alleviate the problems of ground bounce and voltage droop, decoupling capacitors should be connected between ground and each power pin on a device. When the SRAM's output buffers switch, the power terminals will sag due to the effects described above. The function of the decoupling capacitor is to supply this momentary need for current with its stored charge. To do this, it must store a minimum amount of energy. Buffer loading determines this energy and the amount stored is given by the formula:

Where:
   Q = charge stored
   V = applied voltage
   C = bypass capacitance in farads.

   Differentiating this equation yields:

 

By factoring in the worst-case scenario for voltage swing, this equation allows us to calculate the capacitance required to prevent the voltage drops switching output drivers.

 

Capacitor filtering

The main role of decoupling capacitors is to block unwanted noise to and from the power plane. It should be noted, however, that decoupling caps always have a finite, intrinsic resistance and inductance.

 

 

Consider Figure 3, which shows the behaviour of two ideal components: a capacitor and an inductor. Figure 3 represents the reactive parts of the capacitor shown in Figure 2. Note that without any lead inductance or resistance, the resulting capacitive reactance approaches zero with increasing frequency, and the inductive reactance of the ideal inductor, without any stray capacitance, approaches infinity. This means that, in a circuit, a capacitor acts as a low-impedance element only over a limited range of frequencies.

 

 

To extend this frequency range, a second capacitor can be used to bypass frequencies outside the range of the single capacitor. The solid line marked “Expected” in Figure 4 illustrates the resulting impedance curve.

This solution, however, is problematic at intermediate frequencies. Figure 5 shows what happens when two capacitors of different values are placed in parallel. A spike in impedance occurs just above 100MHz, and therefore the goal of obtaining lower impedance across a wider frequency is not fully achieved. On the contrary, the impedance has actually increased in some areas. To lower the impedance across all frequencies, two capacitors of the same value and package size can be placed in parallel with each other. This is a recommended practice so that no peak increase in impedance is realised, however, it may be constrained by available board space.

 

 

 

What frequencies to bypass

It is a common misconception that faster clock rates lead to the need for higher-frequency decoupling. This is only partly true. While the frequencies have increased, the technology for high-speed memories has also been driven to provide faster rise and fall times. Therefore, a 1MHz signal will need the same decoupling as a clock running at 50MHz using the same high-speed buffers. The difference may be that there is more timing margin afforded in the slower-speed system. A rough generalisation suggests that frequencies up to one half of the fastest signal transition rate (rise or fall) need to be bypassed:

It should be noted that decoupling is really a four-part system, comprising the power supply, bulk capacitors, decoupling capacitors and intrinsic capacitance of the board. Each provides decoupling in its respective frequency bands with the power supply addressing the very low frequencies, and the intrinsic board capacitance addressing the high frequencies. The difference between the capacitance is large enough that the spiking effect caused by multiple capacitor value interaction does not occur.

However, between each frequency band there will be small peaks. These peaks will always exist but they can be moved slightly. It is possible to vary the bulk and decoupling capacitance values so that the the four-part system provides a low impedance path, of less than 1Ω, throughout the frequency range. By adjusting the values of the decoupling capacitors, the small impedance peaks can be shifted to allow for the lowest impedance in the frequency ranges of concern.

 

Decoupling capacitors: layout recommendations

SRAM performance is not only affected by capacitors, but also by their connection on the board. When designing with decoupling capacitors, the following guidelines should be considered:

1. Use only one value capacitor for the component
2. Keep decoupling capacitors as close to the component as possible.
3. Use a minimum of one capacitor on each power pin.
4. Keep capacitors on the same side of the board as the component, if possible.
5. Minimise the lead and wiring inductance.
6. Ensure that the capacitor value meets the voltage swing requirements, and that it provides a low-impedance path to ground in the intended frequency range of the application.
7. Long, narrow PCB traces should be avoided because they increase inductance.

 

PCB layout considerations

The traces and planes that comprise a PCB can be separated into two categories: There are pathways for the power source and there are traces required to carry the actual signals, both of which directly affect system integrity.

Power planes are large sheets of a conductive material that typically reside on entire PCB layers. They provide four functions to the circuit:

1. A low-impedance path for power from its source to the components on the PCB.
2. A physical channel to vent and move heat from the components.
3. Electrostatic shielding between the electromagnetic fields of signal traces that run on both sides of the planes.
4. A sheet capacitance for the ground plane that exists on other layers of the PCB. This in turn provides additional AC bypassing within the power circuitry of the PCB.
   The primary function of a power plane is to reduce the resistance that causes a voltage drop between component and power source. The thickest power plane available will reduce the DC resistance and AC inductance drops. The drop in DC resistance allows the power supply to reach the component cleanly, while the reduction in AC inductance provides a low-impedance path for signal return currents. As a secondary benefit, the thicker plane also increases the ability to sink heat out of the component.

The sheet capacitance that the power plane provides is proportional to its size, its distance from the ground plane, and the dielectric constant of the material between planes. It has the benefit of providing bypass capacitance, particularly at the high frequencies. While it is far from being sufficient to provide all of the bypassing needs of a high-speed logic design, it should be utilised to its maximum. The capacitance of the planes can be calculated with the following equation:

Where:
   ER = the relative dielectric constant
   N = number of plates
   A = area of one side of one plate in square inches
   t = thickness (separation of plates) in inches

For example, using a 10-inch by 10-inch FR-4 board with an ER of 4.1 and 0.005-inch separation between the power and ground plane, the capacitance is calculated as:

This is equivalent to 184pF per square inch. Table 1 shows the dielectric constants for several common materials used in PCB design today. It is always advisable to consult your fabricator for the precise ER value, since different epoxies are used when constructing a PCB. Dielectric constants of PCBs also change with frequency, as shown in Table 1.

 

Vias

Vias are commonly used to connect the power plane to the power traces that ultimately attach to the power pins of the components. These can, however, have an impact on the power signal quality.

Vias typically produce a higher resistance than a copper trace and the resistance of a via changes based on the thickness of the copper that is plated in the via hole.

Vias also add inductance to the power trace. This inductance causes high-frequency noise that is present on the power plane to stay on the plane (which is good), but it also isolates the capacitance of the power plane from the components on the other ends of the vias. Filling vias with solder, using heavy plating, enlarging their size and using multiple vias per power connection can lower the resistive and inductive parasitic effects.

Using a via to route to another plane diminishes signal quality. Vias should therefore be avoided as much as possible. If vias have to be used in a highspeed design, make them as large as possible, and plate external layers with the maximum thickness of copper during fabrication.

 

Power traces

Not unlike vias, traces also have some amount of resistance, capacitance, and inductance. The overall resistance must be kept to a minimum to avoid voltage drop on the trace. In order for the power plane to reach the power trace and ultimately the component, a via is required. If connections to the device are made in correct sequence, the combined resistance and inductance of the trace and via will isolate the component’s noise from passing into the power plane.

To achieve this isolation, the power trace must pass from the via to the decoupling capacitor’s pad and then to the component. This order creates an island of protected trace between the decoupling capacitor and the component. It is important to highlight that the trace between component and bypass capacitor should be as short as possible

The goal is to keep the inductance between the devices to a minimum; and a short, wide trace will produce better results than a long, narrow trace.

 

Signal return paths

The power planes play a key role in the return currents of high-speed digital signals. At very slow speeds, the return current follows the path of least resistance. At higher speeds, however, the return currents follow the path of least inductance. This can be on either the power or ground plane, directly below the signal trace. Normally, the return path is on the ground plane on standard PCB designs. When the return current reaches the driving component, the decoupling capacitors provide the bridge to the proper voltage plane. In order to maintain good signal integrity and to minimise crosstalk, a clean, unobstructed return path needs to be provided.

There are a few simple rules to follow for planes: First, it should be as continuous as possible. Placing excessive clearances around holes, or cut-outs in the ground plane, may make fabrication easier but it can cause the return current to travel through a non-optimal path. This increases the inductance of the path and decreases the rise time of the digital signal on the trace.

 

Crosstalk

If crosstalk occurs on a memory signal with sufficiently strong amplitude, a false trigger can occur. Crosstalk should therefore be minimised in the design. Crosstalk between traces is a function of both mutual inductance and mutual capacitance. As illustrated in Figure 6, this is proportional to the distance from the source trace, the speed of the signal edge, and the impedance of the victim trace.

 

The mutual inductance (L_M) can be calculated with the following equation:

Where:
   L = inductance of the wire
   s = separation between the wires
   h = height above the plane

The mutual capacitance (C_M) injects current (I_M) into the victim. This can be calculated as:

Where:
   V_s = source voltage.

To minimise the effects of magnetic field coupling, consider using greater trace separation, shielding the target trace by routing it on another layer, placing protective guard traces, or using differential signalling, commonly referred to as common-mode noise rejection. For more detail please request an extended version of this design note by using the response number shown.

 

 

 

Cypress Semiconductor / DN - SRAM system performance