Designing with MCUs for scalability and low power

To allow easy migration between MCUs Freescale has developed the Controller Continuum that offers an easy path from the entry-level 8-bit RS08 and S08-based microcontroller families up to the high-end 32-bit ColdFire® microcontroller and microprocessor families. The connection point in the Controller Continuum is the 8- and 32-bit compatible Flexis™ series of microcontrollers. This 8-bit and 32-bit range of products offers pin, peripheral and development tool compatibility.

One of the families within the 8- and 32-bit compatible Flexis series is the Flexis QE family, targeted at Ultra-Low-Power (ULP) battery-operated and portable applications. To implement these ULP solutions, Freescale implemented some new features including a new internal clock source with a low power oscillator, clock gating and new CPU Modes.

 

 

Clock management for optimum power

Figure 1 shows the Internal Clock Source (ICS) module common to the QE128 MCUs. This module enables designers to select an external reference clock (ERCLK) from 32kHz up to 16MHz or an internal reference clock (IRCLK) that is trimmable from 31.25kHz to 39.06kHz. The heart of the ICS is the Frequency-Locked Loop (FLL) block which multiplies its input clock up to a maximum 50MHz. The external reference clock can be as high as 16MHz and can be divided by a reference divider (RDIV), which is programmable from 1 to 1024. The FLL can also be bypassed to save power, or if a low-frequency bus is required. A second divider block, the bus frequency divider (BDIV), can divide the clock signal down by one, two, four or eight before it is put onto the ICS output (ICSOUT).

The ICS also controls an independent 1kHz very Low-Power Oscillator (LPO), which can be used by the RTC and the watchdog. Engineers can use this feature to meet EN60730, the standard for automatic electrical controls for household use and similar applications. The key to precision power management using the QE128 ICS is the ability to use the internal oscillator and the external oscillator source for different modules at the same time. This allows designers to optimise power consumption by running each module at the optimum speed to perform the required function with the lowest possible impact on overall system-power budget.

Clock-gating control registers manage the clock gating to the timers, ADC, I²C interface, Serial Communication Interfaces (SCIs), debug module, Flash memory, external Interrupt Request (IRQ), Keyboard Interrupt Module (KBI), analogue comparator, Real-Time Clock (RTC) and Serial Peripheral Interfaces (SPIs). Gating off the clock to unused modules saves precious microamps in the MCU’s run and wait modes, as Graph 1 shows in the case of the MC9S08QE128.

 

 

Optimising CPU modes

Choosing the optimum CPU mode for each stage of the system design can make or break the product’s power consumption targets. To aid optimisation of exit paths, wake-up times and register retention, the QE128 devices add two new power-saving modes in addition to run, wait, stop 3 and stop 2 modes.

The first of these, Low Power Run (LPR), places the voltage regulator into standby. To enter LPR the ICS must be in its lowest power mode and the low-voltage protection system must be disabled, along with the MCU’s internal bandgap and the on-chip in-circuit emulator debug and Background-Debug Controller (BDC) modules. This is necessary because all three modules consume significant power, regardless of the bus frequency.

The second new power-saving mode, Low Power Wait (LPW), can only be entered from LPR mode. Hence the same restrictions on low-voltage protection circuitry, debugging and ICS mode apply. Current draw is typically reduced by 50 percent in LPW mode compared to LPR.

Table 1 compares the key characteristics of the CPU operation modes.

 

 

Conclusion

Careful consideration of the MCU clock-source, clock-distribution and clock-mode selection on a module-by-module basis, combined with judicious use of low-power CPU modes, can help designers meet stringent constraints on power consumption. The features Freescale incorporates are simple in concept and easy to use. In practice, these can halve a system’s power consumption.

 

 

The DEMOQE8 is available to members of the Future Board Club. To apply for the development board, and membership of the Board Club, go to www.my-boardclub.com/manf-offers.htm This offer is free and subject to qualification.

 

Freescale Semiconductor / Design Note