By Colin Weaving
Technical Director, Future Electronics (EMEA)
Over the past ten years, a series of improvements in the design of power MOSFETs, and in the processes used to fabricate them, have enabled MOSFET manufacturers to reduce the on-resistance of their devices by an order of magnitude. Coupled with improvements in device packaging, the unprecedentedly low on-state losses mean that the latest MOSFETs are blessed with remarkably high power and thermal efficiency.
Consumer product manufacturers have benefitted hugely from this, since it has enabled them to provide smartphones, media players, cordless shavers and other such devices that have a longer run-time between battery charges than ever before. Advanced MOSFET technology also underlies a new generation of products such as high-performance portable power tools and e-bikes that simply could not have been realised even a few years ago.
On-resistance, then, has seen dramatic improvements. It seems, however, that this might have come at the cost of the Safe Operating Area (SOA). The marketing literature provided by MOSFET manufacturers gives far greater prominence to on-resistance and other parameters than to the SOA. In fact, however, this parameter is extremely important when designing circuitry which operates in a MOSFET’s linear region for more than a very short interval.
And unfortunately, an unwanted consequence of the techniques used to minimise on-resistance is that the SOA tends to shrink. Since this imposes tighter constraints on the currents that can flow through the MOSFET, it has become more important than ever that system designers should take due account of the SOA, if they are to guarantee the long-term reliability of the device and its host product.
Pinpointing the danger area in a MOSFET’s operation
To show why SOA is such an important parameter in a MOSFET, it is helpful to explain the basic operation of the device. As the stylised output curve in Figure 1 shows, a MOSFET can be in any one of three ‘areas’ or modes of operation: the Off state, the linear region and the saturation region.
The MOSFET is turned on by applying a gate-source voltage, VGS, to the semiconductor material. Below the threshold voltage value, the channel is depleted and no drain current can flow. In effect the device is off.
As soon as VGS exceeds the threshold voltage value, an inversion layer, or channel, forms and current can flow from the drain to the source, ID. The MOSFET now operates in its linear region, in which current is proportional to the drain-source voltage, VDS. In this linear area, both voltage and current rise at the same rate, and therefore the MOSFET is handling a rising amount of power.
At a certain value of VDS, however, this effect ceases: at first, the slope of the curve flattens while remaining somewhat linear. This is due to a widening of the depletion region near the drain terminal, causing the channel to become less conductive. Eventually the channel is clamped, at which point the MOSFET has entered the saturation region, in which the drain current/drain-source voltage curve is flat: the drain-source voltage may now rise without any accompanying rise in drain current. Figure 2 shows the way the channel changes as the MOSFET moves from the Off state to the fully On state.
As Figure 1 shows, a MOSFET supplies its maximum output power when it is in the saturation region. Applications – and there are many of them – in which the most important requirement is to maximise power density (for cost and space reasons) therefore operate the MOSFET in the saturation region as much as possible, and seek to minimise the amount of time spent in the linear region.
Motor drives and switching power supplies, for instance, prize fast-switching MOSFETs which offer very short rise times, so that the MOSFET makes the transition from the Off state through the linear region to the saturation region quickly. And MOSFET manufacturers have also devoted considerable efforts to improving the on-resistance of their products when operating in the saturation region.
Some applications, however, require a power MOSFET to stay in the linear region, or to pass slowly through the linear region. For these applications, the focus on reducing on-resistance in the saturation region has a marked drawback, since it also tends to shrink the SOA in the linear region. The control switch in a Power-over-Ethernet (PoE) power supply, for instance, has to act as a current limiter to protect the circuit from inrush currents when switching on, or in the event of a fault. This requires sustained operation, for a period of a few milliseconds, in the linear region. Load switches, ORing circuits and hot-swap cards have the same requirement.
Using SOA data to manage operation in the linear region
Of course, any electronics component may be rendered inoperable by the application of excessive power to it. But a MOSFET is particularly vulnerable to the risk of excessive power, because the applied power causes self-heating, leading to thermal runaway in the linear region.
This is why MOSFET manufacturers publish a safe operating curve for each device, showing what can safely be done with a MOSFET in both the linear and saturation regions of operation, both at DC and in pulsed mode.
In the SOA curve for the PSMN1R0-30YLC from NXP Semiconductors shown in Figure 3, the vertical boundary on the right represents the maximum value of the drain-source voltage. The slope on the left shows the current limit set by the device’s on-resistance. The horizontal portion of the curve is the maximum pulsed drain current. The almost parallel declining curves are the maximum drain current for given pulse widths, and for continuous direct current.
NXP’s datasheet describes the device as a ‘30V, 100A’ MOSFET. In fact, the SOA curve shows that the drain current rating is not a single value, but varies as a function of the drain-source voltage.
True, the device can handle 100A DC at below 1V – in other words, when the device is fully on, in the saturation region, as it would be in a hard-switching application. If, however, the device is operating in its linear region then the DC current that can be carried by the device is much reduced. At a nominal 10V for instance in DC operation, the safe current capability falls to 20A for a 100μs period.
At the other extreme, when switched rapidly the device can carry much higher currents. For instance, at pulse periods of 10μs, the SOA curve shows that the device can handle 1kA without damage (though not at very low drain-source voltages). It should be said that this maximum pulsed current is rated for a single pulse, not for repetitive pulses.
The SOA curve, then, shows that the designer has to take into account both the conditions in which the MOSFET will operate when fully on, and in the transition through its linear area, to ensure that it remains at all times within its safe operating limits, otherwise it will suffer long-term damage.
This risk of damage is an inherent feature of the design of today’s MOSFETs. MOSFETs are generally thought of as monolithic slabs of silicon: in fact, they consist of many small cells, the dimensions of which are chosen to optimise for parameters such as size (and hence cost), current-carrying capability and on-resistance.
The reduction in on-resistance in the latest generation of MOSFETs has been achieved by shrinking the cell pitch within the MOSFET’s internal structure, to provide more parallel channels per mm2. But this also heightens the risk of creating local hotspots inside the device. And because the cells are close together, and connection to the metallisation layer is more tenuous, a single overheated cell can easily transfer heat to other cells in close proximity, causing a general rise in temperature in the device as a whole: this can damage or even disable the entire MOSFET.
In fact, the PSMN1R0-30YLC, the SOA curve of which is shown in Figure 3, has in common with many NXP MOSFETs an unusually wide safe area. This illustrates what may be allowable in real-world designs. Other devices may not be so well specified, and greater care will be needed when using them.
Practical measures to ensure safe operation
When selecting a MOSFET, particularly for switching applications, the temptation is to choose the part with the lowest on-resistance and gate-charge values at a given price point, in order to maximise power efficiency.
As has been shown, however, measures to reduce on-resistance also tend to narrow the SOA. And any failure to take account of the SOA of the device, and to fully analyse its excursions from the saturation to the linear region of operation, can impair the robustness of the system design.
To widen the effective SOA, designers might choose to:
- reduce the ambient temperature, for instance by implementing forced-air cooling
- reduce junction temperature, through use of a heat-sink affixed to the MOSFET
- reduce the time in transition from the linear region to the saturation region by use of a dedicated gate-driver FET
In many cases, however, the best course might be to choose a device with a wide SOA, and accept a small trade-off in the on-resistance value. The market offers devices which are optimised for a wide linear-region SOA, while still offering very good performance in other parameters. NXP’s range of NextPower Live MOSFETs are an example of this type of device, benefitting from wide cell boundaries and a large area of source metal. This family of MOSFETs provides an extremely wide SOA curve while offering good on-resistance.