Lattice Semiconductor – Comparing circuit board power management architectures

pg8-Lattice
Logo_Lattice
Power management architectures used in circuit boards can be broadly classified into five types, as shown in Figure 1 through to Figure 5. Some designs combine one or more architectures to overcome the individual limitations of each architecture. Typically, circuit-board payload components (ASIC/SOC/CPU) and the input power supplies determine both the power network as well as the management of DC-DC converters used in that power network.

The term power management in this context refers to:
1. Rail-voltage fault monitoring, measurement and sequence control of DC-DC controllers used in the power network
2. Generation of digital control signals such as reset and power OK signals for the payload devices.

In addition, most circuit boards use a Control PLD (C-PLD) to integrate other housekeeping functions such as JTAG, I2C, legacy logic, level translation bridging and other board control functions. This control PLD may be a macrocell-based PLD; a Complex Programmable Logic Device (CPLD); or a small FPGA.

This article uses a typical hierarchical power network to compare different power management architectures.

In this power network three classes of DC-DC converters are used:
1. Device supplies – used exclusively to power the payload devices
2. Board common supplies – to generate voltages shared between multiple payload devices
3. Input supplies – to convert board input supply voltage to main board rail used by all DC-DC converters

The following section examines five basic power management architectures. The table at the end of this article maps major power management design considerations vs architectural benefits.

Fig. 1: power architecture #1 – power management and housekeeping by control PLD

Fig. 1: power architecture #1 – power management and housekeeping by control PLD

Control PLD (C-PLD) monitors the supply status using power-good signals for control signal generation. The sequencing algorithm implemented in control PLD controls the DC-DC converters through their enable signals. CPLD designs are implemented in VHDL or Verilog.

Pros:

  • Low cost
  • Scalable sequencing
  • Single design environment
  • Event-based architecture

Cons:

  • High C-PLD I/O count and board congestion
  • Increased cost for telemetry support
  • Reduced reliability due to unreliable power-good fault detection
  • Requires digital design

dividor

Fig. 2: power architecture #2 – hardware management system implemented using control PLD and power-manager ICs

Fig. 2: power architecture #2 – hardware management system implemented using control PLD and power-manager ICs

Power manager ICs monitor the voltage and control sequencing. C-PLD monitors the supply status using power-good signals for control signal generation. Power manager designs are implemented using GUI and C-PLD designs with VHDL or Verilog.

Pros:

  • Low C-PLD I/O count
  • Low board congestion
  • High power-management reliability

Cons:

  • Expensive solution
  • Difficult to scale sequencing/partition across power managers
  • Design spread across multiple tools (GUI + VHDL/Verilog)

dividor

Fig. 3: hardware management system implemented using control PLD and MCU

Fig. 3: hardware management system implemented using control PLD and MCU

A microcontroller uses PMBus to perform time-based sequencing of digital DC-DC converters (DPOLs). Housekeeping functions, controlling of DC-DC converters without PMBus interface (APOLs) and event-based sequencing of DPOLs are handled by the C-PLD. Power-management designs are implemented using microcontroller software and the C-PLD design with VHDL or Verilog.

Pros:

  • Scalable (for time-based sequencing only)
  • Reduced debug time due to debug utilities
  • Routing congestion reduced around DPOLs
  • Modified with firmware updates

Cons:

  • More expensive
  • Difficult to scale for event-based sequencing
  • Multiple design tools – Verilog/VHDL, software
  • Mix of APOL and DPOL requires hybrid control solution

dividor

Fig. 4: power management and housekeeping by C-PLD with on-chip ADC

Fig. 4: power management and housekeeping by C-PLD with on-chip ADC

C-PLD with an ADC is used to sample all voltages to overcome issues with inaccurate power-good signal. The C-PLD implements power management using on-chip soft/hard processor core, and housekeeping functions using logic. Power management implemented using software and other housekeeping functions are implemented using VHDL/Verilog.

Pros:

  • Scalable solution
  • Reduced design time as power-management and housekeeping functions are together
  • Telemetry support

Cons:

  • Needs CPLD with higher density and higher I/O count
  • Increases circuit-board congestion
  • More expensive
  • Requires digital engineer to design power

dividor

Fig. 5: the L-ASC10 (ASC) remote sensing and controlling element

Fig. 5: the L-ASC10 (ASC) remote sensing and controlling element

C-PLD uses an external Analogue Sense and Control (ASC) device to sample all voltages through the serial bus. C-PLD also controls DC-DC enable signals via the ASC through the serial bus. The C-PLD also implements both power management and housekeeping functions. Power management and housekeeping functions can be implemented using GUI or VHDL/Verilog or both.

Pros:

  • Lowest C-PLD I/O count
  • Least board congestion
  • Single design environment
  • Scalable
  • Reduced overall cost because ASC integrates voltage, current and temperature-monitoring function
  • Reduced design time as power management and housekeeping functions are together
  • Reduced debug time due to debug utilities

Design considerationsCPLDCPLD + Power ManagerCPLD with On-Chip ADCCPLD + MCU + PMBusCPLD + ASC
CPLD I/O utilisation for power managementHigh Medium High Low Low
PCB routing congestionHigh Medium High Low Low
Need to route low-voltage analogue signals to a central location on a PCBNo No Yes No No
Ease of use of the architecture from simple to complex boardsEasy Difficult Medium Difficult Easy
CPLD logic overhead due to power managementMedium None Very high LowMedium
Voltage measurementNo YesYesYesYes
Ability to prevent on-board payload device operation under faulty power-supply conditionsPoor Better Best PoorBest
Power-management design methodologyVerilog/VHDLAnalogue GUI Verilog/VHDLC++ or Verilog/VHDLAnalogue GUI or Verilog/VHDL or both
Design tools – power engineer friendly?No Yes No No Yes
Availability of board power-management section debug toolsNo Limited No Limited Yes
Time required for debugging board power-management sectionHigh Medium High Medium Low
Overall cost of implementation Low High High High Low

As seen from the table to the left, using the Lattice MachXO2/3 CPLDs and ASC ICs provides the optimal solution for power management. In addition, customers can integrate circuit board temperature-management functions to the power-management functions to further reduce overall cost, development and debug times.
 

logo_FTMBoardClub
Orderable Part Number: LCMXO2-7000HE-B-EVN | Buy Now
 

Leave a Reply

Your email address will not be published. Required fields are marked *

Protected by WP Anti Spam