Intersil – Design considerations for high-speed RS-485 data links

pg10_intersil_image1

IntersilLogo
Designers of high-speed data networks are continually striving to achieve higher data rates over longer transmission distances, and under ever harsher conditions. Network equipment today has to be able to withstand electrically noisy environments, large ground-potential differences and high operating temperatures.

The applications that are stretching the capabilities of reliable high-speed networks to the limit include:
• Data-acquisition systems in seismic networks
• GPS data-transmission links in telecoms basestations
• Video transport in traffic-monitoring systems
• PLC communication in factory-automation equipment
• Motor encoders

The RS-485 standard technology (also known as EIA/TIA-485) is commonly used for industrial high data-rate networking deployments. This Design Note offers a series of design tips for developers of high- speed RS-485 system and bus nodes.

RS-485 transceiver requirements
To counteract the potential for signal degradation in RS-485 transmissions, designers should specify high-speed transceivers which offer a high differential-output voltage, VOD, and small skews.

A high driver VOD balances the reduction in signal amplitude caused by cable attenuation, data encoding and common-mode loading, and provides a sufficient noise margin at the remote receiver inputs.

In low-voltage designs, it is important to be aware of the pitfalls in the use of so-called poor man’s 3V transceivers, as these have poorly designed output stages which only provide RS-485-compliant output voltages at supply voltages of ≥4V, as shown in Figure 1.

pg10_intersil_image2

Fig. 1: PM3V transceiver operating with a 3.3V supply / Fig. 2: Intersil 3V and 5V high-speed transceivers greatly exceed the RS-485 minimum VOD of 1.5V

At lower supply voltages, transistor efficiency drops markedly, producing a VOD as much as 40% below the 1.5V minimum required by RS-485 equipment. Output voltages at such a low level will not yield a sufficient noise margin to trigger a remote receiver.

Figure 2 shows a selection of Intersil high-speed transceiver families which offer a very high output-drive capability. They produce a minimum VOD range from 160% of the specified 1.5V minimum at a 4.5V supply down to 100% at a 3.0V supply, thus delivering true 3V RS-485- compliant drive capability. The typical VOD measured at the highest operating temperatures actually exceed the RS-485 requirements by 27% at 3V and by 70% to 93% for 5V transceivers.

In addition, a small pulse skew minimises the transceiver’s contribution to the data link’s total jitter budget. All Intersil high-speed transceivers are specified with a maximum pulse skew of 1.5ns. A low part-to-part skew is also important in synchronous applications, in which the clock and data signals come from different transceivers and tight clock-to-data
timing must be maintained.

Part-to-part skew is measured between any two transceivers under identical temperature and supply-voltage test conditions. Intersil transceivers, which benefit from very low process variations, offer precise switching characteristics, and it is the only vendor of high-speed RS-485 transceivers specifying a part-to-part skew as low as ≤4ns.

More robust operation
To ease the process of network maintenance or the replacement of defective bus nodes during network operation, Intersil high-speed transceivers provide hot-plug capability as well as ESD immunity conforming to the IEC 61000-4-2 standard.

Hot-plug capability ensures that during power-up and power-down, the transceiver’s driver and receiver outputs maintain high impedance, regardless of the logic state of the Enable pins DE and /RE. This prevents disturbances on the bus, which otherwise could falsely trigger other bus transceivers. It also gives the local node controller time to stabilise and drive the RS-485 control lines to the desired logic states.

pg10_intersil_image3

Fig. 3: ESD transient comparison between IEC 61000-4-2 and HBM

The use of IEC 61000-4-2 ESD protection circuitry safeguards the transceiver against damage from electrostatic discharges caused by field and maintenance personnel. These discharges occur in uncontrolled ESD environments, so to mimic these conditions an IEC-ESD test generator creates transients with much shorter rise times and pulse widths and much higher peak currents than a Human Body Model (HBM) ESD generator, which is intended to simulate ESD-controlled environments only, as shown in Figure 3.

ESD protection structures designed for IEC 61000-4-2 can often tolerate HBM test voltages of up to 2.5 times their IEC test voltage. Thus an ESD structure designed for 8kV IEC contact discharge should be able to withstand a HBM contact discharge of up to 20kV. All Intersil high-speed transceivers are rated for the more stringent IEC ESD requirements.

pg11_intersil_image1

Fig. 4: Suggested bus-node layout with an FPGA operating as the controller, and including an ISL3159 transceiver

Bus-node design tips: component layout
The pin-out of an RS-485 transceiver is tailored for a straightforward node design, as the bus terminals (A/Y, B/Z) are located on one side of the IC, and the single-ended data lines (DI, RO) and control lines (DE, /RE) are on the opposite side, as shown in Figure 4.

High-speed bus nodes require the application of controlled- impedance transmission lines to suppress EMI. On the bus side, the differential impedance of the bus traces must match the characteristic impedance of the transmission medium (100Ω or 120Ω). On the control side, the line impedance of the single-ended traces is commonly set to 50Ω.

Controlled-impedance lines may be created by the use of well-defined trace geometries (length, width, height, and trace spacing) and close electrical coupling with a low-inductance reference plane, either ground or power. This is easily accomplished with a bus node consisting of a transceiver and controller. However, with the addition of lightning- protection components, such as the surge resistors and transient suppressors shown in Figure 4, the design becomes more complicated.

In this case, the spacing of the differential traces is widened, which causes the differential impedance to deviate from its intended value. This constitutes an impedance discontinuity which generates reflections and EMI. While discontinuities might be unavoidable, they should be grouped together to keep the area they occupy small.

To calculate the required trace geometries accurately, it is advisable to use a field solver programme. This software tool calculates the characteristic impedance, signal speed, crosstalk and differential impedance. It can also solve for a geometry with almost any arbitrary cross-section. In addition to first-order terms such as line width, dielectric thickness and dielectric constant, second-order terms such as trace thickness, solder mask and trace etch-back can be taken into account.

Fig. 5: Recommended four-layer stack for a bus-node design

Fig. 5: Recommended four-layer stack for a bus-node design

Layer stack
At least four layers are required to create a PCB design that produces low EMI, as shown in Figure 5. Layer stacking should be in the following order (top to bottom): high-speed signal layer, ground plane, power plane and control-signal layer.

Routing the high-speed traces on the top layer avoids the use of vias, with their accompanying inductances, and allows for clean interconnects from the bus connector to the transceiver bus terminals, and from the transceiver’s high-speed single-ended data lines to the subsequent node- controller circuit.

Placing a solid ground plane beneath the high- speed signal layer establishes controlled impedances for transmission-line interconnects and provides an excellent low-inductance path for the return flow of current. Placing the power plane beneath the ground plane creates additional high-frequency bypass capacitance.

Routing the slower control (enable) signals on the bottom layer allows for greater flexibility, as these signal links usually have some margin to tolerate discontinuities such as vias, and the separation nearly eliminates crosstalk from the high-speed data traces.

Intersil transceivers for high-speed networks
Intersil supports a wide range of RS-485 applications with a portfolio of high-speed and ultra-high-speed transceivers. The devices help designers to overcome the potential for signal degradation by providing an exceptionally high output-drive capability and highly accurate switching performance when operating from either 3.3V or 5V power supplies. Highly robust, these parts can support hot-plug operation and are immune to ESD strikes up to 16kV according to the IEC 61000-4-2 standard.

Intersil transceivers are available in 3mm x 3mm DFN packages and support a wide operating-temperature range of -45°C to 125°C.

Leave a Reply

Your email address will not be published. Required fields are marked *

Protected by WP Anti Spam