Cypress Semiconductor’s static RAM (SRAM) ICs provide the high-speed read/write operation and high reliability required in wireless access points and other devices containing an embedded processor or microcontroller.
An SRAM density of 36Mbits is available from Cypress in the CY7C1440KV33 and CY7C1440KVE33, which are organised as 36 x 1Mbit cells. Cypress also supplies the CY7C1442KV33, organised as 18 x 2Mbit cells. They achieve a maximum access time when operating at 250MHz of just 2.5ns.
These SRAM devices feature advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge-triggered clock input. The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable, depth-expansion chip enables, burst control inputs, write enables and global write functions. Asynchronous inputs include the output enable and the ZZ pin.
Addresses and chip enables are registered at the rising edge of the clock when either the address strobe processor or the address strobe controller are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin.
Write cycles may be one, two or four bytes wide as configured by the byte-write control inputs.
• All inputs and outputs compatible with the JEDEC standard JESD8-5
• Registered inputs and outputs for pipelined operation
• 2.5V or 3.3V I/O power supply
• High-performance 3-1-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single-cycle chip deselect