Microsemi – Motor-control systems: choosing an FPGA for efficiency, performance and scalability

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Electric motors collectively consume a substantial portion of the world’s electricity generation. According to the research firm IHS Technology, the cost of the electricity used to power a motor makes up 96% of its lifetime costs.

In an attempt to reduce the environmental impact of electric motors, regulators have imposed more stringent energy standards. At the same time, manufacturers are scrutinizing their considerable contribution to the total cost of ownership of electric equipment.

This has led to more complex motor-control designs which use sensored and sensorless feedback loops and advanced algorithms for more precise control and higher efficiency. Motor designers also must support changing industrial control standards and technologies, while providing system features that ensure safety, scalability and reliability.
Meeting the twin goals of energy efficiency and enhanced system-level capabilities requires adequate processing power to run algorithms, together with flexible and scalable system architectures.

Non-volatile, secure and low-power Flash-based System-on-Chip (SoC) FPGAs enable designers to meet both challenges, by delivering the necessary horsepower with a combination of both inherent and layered security and reliability with protected communications for Internet of Things (IoT) applications. They also provide the ability to quickly and easily scale from small-footprint to feature-rich custom motor designs in a variety of multi-axis or high-RPM applications.

The challenges
While traditional designs use simple scalar control, high-efficiency motors use Field-Oriented Commutation (FOC) across all torque and speed ranges to improve efficiency.

Because it is current-controlled, FOC can also optimise power-inverter circuitry and the motor footprint. It uses feedback looping, with or without sensors, and sophisticated algorithms to regulate important motor behaviours including speed, position or angle, torque, current, and flux.

While microcontrollers and DSPs have traditionally been used to process algorithms in single- and dual-axis designs, their processing capabilities are not keeping up with the increased demands of multi-axis or high-speed motors. Adding to the challenge, motor efficiency is rarely the only concern, especially in connected factories. Today, the IoT demands secure communications, which Flash-based FPGA architectures are ideally placed to address.

Fig. 1: SmartFusion2  an FPGA SoC which can be used in motor-control applications

Fig. 1: SmartFusion2 an FPGA SoC which can be used in motor-control applications

Power migration
Looking at the motor’s power system, there is also a trend to migrate from IGBTs to Silicon Carbide (SiC) power MOSFETs. SiC devices withstand higher temperatures, and therefore enable the use of smaller and cheaper heat-sinks, and offer better thermal conductivity, resulting in higher power densities. In addition, since they support switching frequencies higher than 100kHz, they enable the use of smaller magnetics at the inverter stage. This reduces the motor manufacturer’s Bill-of-Materials (BoM).

On the control side, DSPs and MCUs struggle with high switching frequencies. Some DSPs might optimise a few channels for high- frequency switching, but they still lack the ability to quickly adapt to changing requirements, and to add more PWM channels to control the power electronics stage. In fact, this function is often offloaded to an
FPGA. ASICs and ASSPs suffer from the same flexibility and scaling drawbacks.

By contrast, Flash-based FPGAs offer greater performance than MCU- or DSP-based solutions for high-speed, low-latency algorithm processing, while enabling the integration of additional system functionality to further reduce the BoM. Designers can use the Flash- based FPGA to provide higher capabilities when an MCU or DSP has reached the limit of the switching frequency or number of PWM channels that it can support.

As Figure 1 shows, a Flash-based SoC FPGA with an ARM® Cortex®-M3 core can be used for motor control and monitoring functions. The FPGA fabric is used for hardware acceleration of motor- control functions to improve performance, and for design flexibility. Motor-control algorithms can be offloaded to the FPGA for faster parallel processing, with intelligent partitioning to ensure that all communications protocols in the MCU sub-system can be handled with no effect on the calculations running in the FPGA.

Enhancing this FPGA solution are modular suites of plug-and-play IP blocks which implement all mathematical motor models. Developers can determine which IP blocks to accelerate in the FPGA fabric so that they can meet all the challenges of algorithm processing.

These solutions ensure low-power operation while enabling developers to optimise their systems for reliability, safety and security using a simplified design process that speeds time to market while providing the flexibility and scalability to meet evolving needs.

Low-power operation
FPGAs used for motor-control designs must reduce both static and total power, especially at high frequencies and temperatures. FPGAs which feature an embedded single-transistor Flash cell offer an advantage over alternatives that use a six-transistor SRAM cell, which must be configured from an external ROM during power-up.

The latest Flash-based FPGA solutions also use a comprehensive approach to minimising power consumption: it encompasses process technology, architecture and the design of configurable logic, as well as embedded features including a hardened processor core, 5G SERDES, DDR2/3, TSE, DSP blocks, and special power modes. This approach results in 50% lower total power and 10% lower static power than SRAM-based FPGAs.

Reliability, safety, and security
In general, an FPGA is more reliable than an MCU for implementing motor-control and network functions in which deterministic timing is important. While there can be milliseconds of timing variability in a microcontroller, there are a few nanoseconds or less in the FPGA.

In addition, the best choice for security is a Flash-based rather than an SRAM-based FPGA, because it stores configuration information on- chip in non-volatile memory – the bit stream is never exposed at start- up. It also provides immunity to single-event upsets which can change the configuration contents of SRAM cells.

Some Flash-based FPGAs can also serve as root-of-trust devices with key storage capability to protect connected industrial IoT systems from cloning, tampering and other malicious attacks. These FPGAs address security needs with features such as a Physically Unclonable Function (PUF) from which the Private Key in a Public/Private Key scheme can be derived for implementing M2M authentication using Public Key Infrastructure (PKI).

Other features include cryptographic accelerators, a random number generator, hardware firewalls to protect CPU/DSP cores, and Differential Power Analysis (DPA) countermeasures that, together, allow security to be layered as needed throughout the system to protect the hardware and data.

Fig. 2: By sharing the use of common IP blocks  an FPGA can make efficient use of its hardware resources

Fig. 2: By sharing the use of common IP blocks an FPGA can make efficient use of its hardware resources

A modular approach
Modular and performance- oriented suites of IP blocks enable algorithms to be implemented with plug-and- play simplicity. Designs can easily be ported across multiple platforms to speed time to market. All IP blocks are tested in simulations on actual hardware to ensure precise torque output, and easily integrated to create task-specific modules.

Each block facilitates sharing of common FPGA resources for the most efficient chip utilisation, as shown in Figure 2. The IP suite also includes all basic building blocks, such as Clarke and Park transformations, proportional integral (PI) controllers for control-loop feedback, and space vector PWM.

Flexibility and scalability
A modular IP suite also simplifies customisation and scaling to support different combinations of multi-axis motors or high-RPM solutions, while meeting evolving regional technology standards. The more compact the IP blocks, the more headroom there is to support integration efforts.

An IP suite running on an FPGA can be scaled to drive from two Brushless DC (BLDC) motor or stepper motor channels to a six-axis solution, or to extend motor performance beyond 70,000rpm.

One way to scale to multi-axis FOC control is to time-division multiplex each FOC loop within the device so each of the motors can be individually controlled for different reference speeds and torque requirements. Everything is implemented in the FPGA fabric, leaving the microprocessor sub-system available for running a communication protocol stack, providing the human-machine interface, or other tasks.

Designers of electric motors must meet energy mandates while ensuring systems can scale and adapt. Flash-based SoC FPGAs provide an increasingly attractive alternative to DSPs, MCUs, ASICs and ASSPs, combining the necessary processing horsepower with hardware and software programmability plus broad options for accelerating and intelligently partitioning
functionality.

Flash-based FPGAs add the benefit of inherent security, and can serve as the root of trust for secure IoT communications in the connected factory.

Orderable Part Number: M2GL-EVAL-KIT

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