The PSoC 6 is based on Cypress’s ultra low- power 40nm process technology, and offers a power-efficient and flexible architecture, including the security features required for next-generation IoT devices.
The PSoC 6 architecture fills a gap in the market between power-hungry and higher-cost application processors and performance- challenged, single-core MCUs. The dual-core ARM® Cortex®-M4 and Cortex®-M0+ architecture lets designers optimise for power and performance simultaneously. The Cortex-M4 core draws 22μA/MHz of active power and the Cortex-M0+ core just 15μA/ MHz. Dynamic voltage and frequency scaling further contribute to the device’s unmatched power efficiency.
The dual-core architecture also enables designers to optimise system operation to take advantage of low-power states, using the auxiliary core as an offload engine while the main core sleeps.
Design flexibility is an advantage of the programmable PSoC architecture familiar to users of previous PSoC devices, and it is found also in the PSoC 6 MCU: software-defined peripherals can be used to create custom analogue front-ends or digital interfaces for innovative system components such as electronic-ink displays. Wired and wireless connectivity options are available, including a fully integrated Bluetooth® Low Energy 5.0-compatible radio, and Full-Speed USB.
In addition, the PSoC 6 MCU architecture features the latest generation of Cypress’s CapSense® capacitive-sensing technology, enabling designers to create robust, reliable touch- and gesture-based interfaces.
The security capabilities integrated in the PSoC 6 MCU architecture are a particularly attractive feature for designers of IoT nodes. It provides a hardware-based Trusted Execution Environment (TEE) with secure-boot capability, and integrated secure data storage to protect firmware, applications and secure assets such as cryptographic keys.
PSoC 6 implements a broad set of industry-standard symmetric and asymmetric cryptographic algorithms, including Elliptical- Curve Cryptography (ECC), Advanced Encryption Standard (AES), and Secure
Hash Algorithms (SHA 1,2,3) in an integrated hardware co-processor designed to offload compute-intensive tasks. The architecture supports multiple, simultaneous secure environments without the need for external memories or secure elements, and offers scalable secure memory for multiple, independent user-defined security policies.
The architecture is designed and configured using Cypress’s PSoC CreatorTM integrated design environment and the ARM ecosystem.
- 1Mbyte of Flash memory
- Execute-in-place Quad-SPI Flash interface
- 288kbytes of SRAM
- 2.4GHz RF transceiver
- BLE v5.0 link layer
- Digital audio interfaces such as I2S and pulse-density/pulse-code modulation
- IoT devices
- Handheld products
FTM readers may register as a PSoC 6 early adopter online. Click here.