Nexperia – Qrr the forgotten parameter in power efficiency

By Mike Becker
International Product and Marketing Manager, Power MOSFETs, Nexperia

Low-cost power supplies are used in abundance to power a wide range of consumer and industrial applications, such as mobile phones, tablet and notebook computers, rechargeable power tools and LED lighting, to name a few.

The efficiency of a power supply is often the most important design factor, whether high efficiency is needed to meet legislative requirements, or to reduce the dissipated heat and thereby enable the design of a smaller, lighter end product. Choosing a synchronous MOSFET to meet all of the requirements can be a bewildering task.

When selecting a MOSFET for a switching application, engineers often look at the obvious datasheet parameters first. For example, what size and type of package is needed? What voltage is needed (average and peak)? Also, what is the maximum output current? This determines the I2R losses at the rated load current, and hence the MOSFET’s on-resistance also.

Maybe a few of the dynamic parameters will be considered also, for example, gate charge, Qg and Qgd, can be a good indicator of the expected gate losses. The Qg Figure Of Merit (FOM) is also a good indicator of a MOSFET’s efficiency in a switching application, and the MOSFET’s capacitance, Ciss, Coss, Crss, can help to indicate whether drain-source spiking and gate bounce will be a problem. Low capacitance can contribute to higher efficiency also.

There is another parameter, Qrr, which can generally be found lurking at the bottom of the datasheet and is often ignored. In applications where current flows through the MOSFET’s body diode, for example, in a synchronous rectifier and in free-wheel applications, then the reverse recovery charge, Qrr, causes some significant problems as discussed below, which the design engineer needs to carefully address.


Fig. 1: Qrr is stored charge in the body diode

What is Qrr?
Qrr is stored charge, measured in nC, and is caused by charge carriers accumulating in the body
diode’s PN junction when the diode is forward biased, as shown in Figure 1.

Beware of Qrr!
Due to the dead-time needed in most applications, current flows through the body diode twice for every switching cycle.

In the first instance, we can consider what happens just before the sync-fet is turned on. Since current will be flowing through the body diode during the dead-time, then some of the load current becomes trapped as stored charge, Qrr.

As the sync-fet is turned on, then the stored charge
is dissipated internally within the MOSFET. Therefore, a proportion of the load current is lost due to the Qrr effect and becomes an I2R loss within the sync-fet.


Fig. 2: Reverse recovery time is a parameter specified in the datasheet

In the second instance, the MOSFET’s body diode becomes reverse biased once again when the high-side MOSFET turns on. Additional current, Irr + load current, flows briefly through the high-side MOSFET until the stored charge, Qrr, is fully depleted. The charge depletion is not instantaneous, and the reverse recovery time, Trr, is also quoted on the datasheet, as shown in Figures 2 and 3.


Fig. 3: Qrr is depleted through the FET

Irr typically flows for a few tens of nanoseconds until Qrr is depleted. Irr results in additional I2R losses within the high-side MOSFET, as shown in Figure 4.

Vds spiking
Reverse recovery current, Irr, also interacts with the PCB’s parasitic inductance to create a voltage spike where:
V = L x (di/dt).

The MOSFET should be suitably rated to ensure that the breakthrough voltage rating is higher than the maximum spike; typically an 80% derating is applied. An application with a measured 80V Vds spike would typically require a MOSFET with a breakthrough voltage of at least 100V.

Good PCB layout can reduce the parasitic inductance, L, and choosing a low Qrr MOSFET can help to reduce the di/dt also. If spiking is ignored, then this may result in a higher voltage MOSFET being required.

Gate bounce
When Vds spiking occurs, then designers should also look for gate bounce in their application. Since there is capacitance between all three terminals of a MOSFET, then any spiking at the drain pin will also be capacitively coupled to the MOSFET’s gate pin. In extreme cases, if the gate bounce exceeds the MOSFET’s threshold voltage then the MOSFET can turn on.

Dead-time is usually applied in the gate drive circuits to ensure that the high-side and low-side MOSFET cannot be turned on at the same time. However, when gate-bounce occurs, then the low-side MOSFET is turned on at the same time as the high-side, causing shoot-through current to flow between the power-supply rails, resulting in excessive I2R losses and in extreme cases causing destruction of the MOSFET.

Benefits of low Qrr MOSFETs
MOSFETs are not all the same. A quick comparison of MOSFET vendors’ datasheet parameters for 100V MOSFETs with 4~8mΩ on-resistance shows that there are dramatic differences in Qrr between different vendors.

The Qrr of MOSFETs from other vendors is typically 130% to 300% higher than similar on-resistance MOSFETs with NextPower 100V technology from Nexperia.

Since it is difficult to measure the individual Qrr effects in a typical application, then we rely on simulations to model the effects instead.

Spice simulations for a 7mΩ MOSFET, PSMN6R9-100YSF, show that when Qrr is increased by 2x, the resultant spike voltage can increase by around 8%, as shown in Figure 5.

Choosing a MOSFET with low Qrr can also significantly improve the efficiency, especially at low load current.


Fig. 5: Lower Qrr correlates with lower voltage spikes

In low-power chargers and adapters, where load currents are typically less than 5A, then there is less emphasis on I2R losses, and design engineers should pay more attention to the dynamic losses also.

In conclusion, choosing a MOSFET with low Qrr can result in lower spiking, improved efficiency and reduced EMI emissions, as shown in Figure 6.

NextPower 100V MOSFETs offer very low Qrr as well as competitive on-resistance, and are ideally suited to power supply applications.


Fig. 6: There is a big efficiency gain to be made from specifying a MOSFET with low Qrr


New 100V MOSFETs help improve switching efficiency, increase reliability and reduce EMI in power-system designs

Nexperia has introduced a new 100V family of NextPower MOSFETs which offer much lower reverse-recovery charge,Q , specifications than competing devices. The MOSFETs are
qualified for operation at a maximum junction temperature of 175°C, including the parts housed in a LFPAK56 (PowerSO8) surface-mount package.

The Nexperia NextPower 100V MOSFETs are recommended for applications that require efficient switching and high reliability. Offering low on-resistance values and high avalanche-energy ratings, they are particularly well suited to USB Type-C chargers supporting the USB Power Delivery standard, and to 48V DC-DC adapters.

The devices feature low body diode losses: the Qrr figure for some parts is as low as 50nC, resulting in lower reverse-recovery current, lower voltage spikes and less ringing than earlier NextPower MOSFETs. This in turn allows designers to optimise dead time and thus improve efficiency in power-system designs, while reducing the severity of EMI.

The NextPower 100V MOSFETs are available in TO220 and I2PAK through-hole packages as well as the LFPAK56.

Part NumberPackageMaximum On-resistanceTotal Gate ChargeQrr


  • 27 general-purpose I/O lines
  • 32 general-purpose working registers


  • IoT end nodes
  • User interface in home appliances