Use of the new CTS module enables the designers of communications equipment and other systems to minimise the risk of generating and propagating parasitic noise through the timing circuit. Featuring low phase noise of <-160dBc/Hz at 100kHz, the VFJA9591C provides dual LVCMOS outputs and offers enable/disable and lock-detect functions. The module has a 9.5mm x 9.1mm footprint and is 3.6mm high.
CTS introduced the new module in response to efforts by communications system manufacturers to increase channel capacity and transport speed while keeping jitter noise as low as possible. Noise propagation in networks that operate at high frequencies and high bit rates can create data distortion during signal synthesis or clock recovery stages. Any spurious noise generated while synthesising or recovering a network clock can propagate through the system layers, and might corrupt data packets.
Traditionally, system design engineers have used a multi-stage timing topology which locks, at one end, to a stable low-frequency reference source, and at the other end to PLL circuitry. The PLL multiplies the reference source to higher frequency rates required for data transmission. The VFJA9591C provides an ASIC-based integrated PLL solution which attenuates short-term noise, or jitter, and multiplies low frequencies, while helping design teams to reduce development time and effort.
- Input-frequency range: 10MHz to 200MHz
- Dual-ended output-frequency range: 10MHz to 160MHz
- 85fs jitter at output frequency <100MHz
- 15Hz modulation bandwidth
- 100ns maximum enable/disable time
- Telecoms equipment
- Military communications equipment
- Base transmitter stations
- Autonomous vehicles
- Digital video equipment
- Test and measurement equipment
- Radar systems